In a conventional semiconductor chip having a non-volatile memory that can be written into once, a write pattern for operating a test circuit implemented within the chip is stored in the non-volatile memory in advance. When a PROM (Programmable Read Only Memory) that can be written into once is built inside a chip as a OTP (One Time Programmable) memory used for an encryption key, for example, the cells written into need to be varied from one chip to another because the PROM is used for the encryption key. Thus, conventionally, a write circuit is separately provided, so that the write pattern data can be varied from one chip to another. As a result, the man-hours for designing the test circuit built inside the chip and the area for macros increase.
In order to reduce the man-hours required for designing the test circuit and the area required by macros, the write pattern data may be externally generated and written into the chip at the time of testing the chip. From the viewpoint of writing the write pattern data into the chip from the outside, Patent Document 1 proposes writing data in a predetermined order so that the influence of heat, for example, caused by the write operation is not localized. Patent Document 2 proposes adjusting the duration of time for writing data depending on the volume of the written data. Patent Document 3 proposes providing memories separately for common data and individual data so that either the common data or individual data can be designated.                Patent Document 1 JP54-052933A        Patent Document 2 JP2003-196991A        Patent Document 3 JP2004-199827A        